Calculating machine with key-controlled gates setting function counter states

ABSTRACT

Key-controlled electronic calculating apparatus has a function state counter controlling various arithmetic calculations. The states are established by function keys gating signals to set the counter into predetermined states. Each function key produces a signal of predetermined duration that may comprise a sequence of pulses. The counter states may be controlled by feedback gating signals from a previous counter state.

United States Patent Kitz 1 Feb. 1, 1972 [54] CALCULATING MACHINE WITI'IKEY- [56] References Cited CONTROLLED GATES SETTING UNITED STATESPATENTS FUNCTION COUNTER STATES 3,291,910 12/1966 Nicklas et al...l78/79 x Inventor: Norbert i u g Middlesex SCUIIIO gland PrimaryExaminer-Eugene G. Botz [73] Assignee: Bell Punch Company Limited,London, 148mm"! Malzahn England AttorneyLaurence R. Brown [22] Filed:July 29, 1969 [57] ABSTRACT [21 Appl. No.: 845,831 Key-controlledelectronic calculating apparatus has a function state countercontrolling various arithmetic calculations. The states are establishedby function keys gating signals to set the [52] U-S-Cl ..235/160 counterinto predetermined states. Each function key ..G06f 7/48 produces asignal of predetermined duration that may com- [58] Field of Search..235/160, 145; 340/365; 178/80 Prise a sequence of P The counter statesy be trolled by feedback gating signals from a previous counter state.

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m Gafas wig] PATENTED FEB I I972 SHEET 3 Bf 4 CALCULATING MACHINE WITIIKEY-CONTROLLED GATES SETTING FUNCTION COUNTER STATES This invention hasreference to calculating machines and has particular reference to anapparatus for controlling the function state of the calculating machineby means of keyboard-controlled. gates. Such calculating machines have afunction keyboard which has function keys corresponding with thefunctions or program operations which are possible on the calculatingmachine. Depression of a function, key initiates the generation of anelectrical signal which is unique to that function and which isused tocontrol the function gating circuits used by the calculating machine toperform that function. The electric signal whose generation is initiatedby the depressed function key may be a train of pulses of predeterminednumber and/or predetermined period in time or may be a single pulsegenerated along a line connected between the function key and thosefunction gating circuits controlled by the function key. Depression ofthe digit keys on the digit keyboard of such a calculating machine alsoinitiates functions or programs which are also controlled by theapparatus and which are concerned with the entry of the digit numbercorresponding to the depressed digit keys into a register of thecalculating machine.

An object of the invention is to provide an improved calculatingmachine.

A further object of the invention is to provide an apparatus forcontrolling the function state of a calculating machine by gating into astate counter pulses controlled by a function keyboard.

According to the invention there is provided a calculating machinesimilar to that of my copending US. application Ser. No. 845,811 filedJuly 29, 1969, having an apparatus for controlling by a keyboardfunction circuits of the calculating machine, said apparatus including acounter circuit whose input is connected to a source of function pulsescontrolled by function keys and/or digit keys and whose outputs from thecount states are connected to the function circuits.

A constructional embodiment made in accordance with the invention willnow be described, by way of example with reference to the accompanyingdrawings wherein:

FIGS. 1 and la show a block diagram of part of an electronic calculatingmachine made according to the invention;

FIG. 2 shows a gate of one of the set of gates shown in FIG. I ingreater detail; and

FIG. 3 shows the set of gates 11 shown in FIG. 1a in greater detail.

The FIG. 1 shows an electronic calculating machine made according to thepresent invention. In FIG. 1 a master oscillator I generatesfree-running oscillator pulses GD which are on at H 2v. and off at v.The oscillator l is connected to an input decade 2 which is connected asa Johnson ring circuit. The input decade 2 divides the master oscillatorpulses GD into sequential groups of ten pulses, viz P0, P1, P2, P3, P4,P5, P6, P7, P8 and P9.

The output pulses P0 to P9 from the input decade 2 are internally gatedto give waveforms P0, P and P9, a waveform 9, and a waveform dP9.

Waveform P0 is up (at +12 v.) from the back edge of the P9 pulse to theback edge of the P0 pulse.

Waveform P5" is up from the back edge of P4 pulses to the back edge ofP5 pulse.

Waveform P9 is up from the back edge of P8 pulse to the back edge of P9pulse.

Waveform 9', is up from the back edge of P0 pulse to the back edge of P9pulse.

Waveform dP9" is up from the back edge of P9 pulse to the front edge ofP0 pulse.

The calculating machine has a digit keyboard 5 having l0 normally opendigit key switches (not shown) representing the digits 0-9 respectively,which switches are closed when the corresponding keys (not shown) aredepressed. The normally open contact of the digit key switches (notshown) representing the digits ()9 respectively are connected to thepulses P0 to P9 respectively and theconnections to the movable contactof the digit key switches are connected to a digit gate circuit 7 whichhas an output to a digit highway HW2. The digit gate circuit 7 is resetby a pulse P0. When a digit key (not shown) is depressed to close thecorresponding digit key switch, a digit signal of a train of pulses ofnumber equal to the digit corresponding to the digit key depressed, isrepetitively transmitted along the digit highway l-IWZ until thedepressed digit key is released.

The calculating machine also has a function keyboard 8 which hasfunction key switches(not shown) marked with the following symbols X,"decimal point, con stant," and enter. The function key switches (notshown) marked X," and which control the arithmetical functions ofaddition, subtraction, multiplication and division respectively, aresimilar to the digit key switches and are connected in a similar way toa function gate circuit 9. The output from the function gate circuit 9is connected to a function highway I-IW3. The function gate circuit 9 isreset by a pulse P0. When a function key is closed by depression of thefunction key, the corresponding function signal is repetitivelytransmitted along the highway HW3. The four function signals transmittedalong function highway HW3 are:

on depression of the key, up at the back edge of P7, down at the backedge of P0;

on depression of the key, up at the back edge of P7, down at the backedge of P0;

on depression of the X key, up at the back edge of P3, down at the backedge of P0;

on depression of the key, up at the back edge of P5, down at the backedge of P0.

The minus key also puts out a minus" signal M to the logic gates.

The entry key transmits a CE" signal along the line C.E., when the entrykey is depressed. The decimal point key transmits a DP" signal along theline D.P., when the decimal point key is depressed; and the constanttransmits a constant signal I(" along the line K, when the constant keyis depressed.

A function counter circuit 10 is a decade counter internallyinterconnected so as to have eight count states so that the countercircuit will sequentially count up to eight. An output is connected to arespective count state and the eight count state outputs are labeled inorder of ascending count state as the function positions F0, F1, F2, F3,F4, F5, F6 and F7 respectively. The function position F0 is connected toan IN- VERTER circuit 10a to give an output F0. The function position F0is also connected to a delay circuit 10b to give an output dFO whichcomes up at the back edge of the pulse from the function position F0 andgoes down after a time delay set by the delay circuit 10b. The input ofthe function counter circuit 10 is connected by a highway HW4 to a firstset of gates II which are described in detail later. The outputs of thefunction positions F0 to F7, F0, and dF0 are connected to the input of abuffer circuit in the form of an emitter follower respectively of agroup of 10 emitter followers which are shown as the rectan gles in FIG.In. The outputs of the respective emitter followers are connected to thefunction circuits which are controlled by the function position ashereinafter described. Each function position corresponds to a functionperformed within the calculating machine and is connected to thefunction circuits which perform the function.

The functions controlled by the function positions are:

F0-display or wait F4-subtracl Fl-clear F5-divide FZ-index F6- not usedFJadd F7-mulliply A timer circuit 12, which is a seven-position Johnsonring circuit is internally interconnected to have 13 count stages whichare labeled in order of ascending count stages T0, TD, T1, T2, T3, T4,T5, T6, T7, T8, T9, T10, T11. The timer circuit 12 is drivencontinuously by P9 pulses from the input decade 2 so that the countstate outputs are sequentially and continuously generated and each countstate output lasts from the back of the P9 pulse to the back edge of thenext P9 pulse.

A visual display 14 includes 10 number tube circuits each having anumber tube 16 and 10 decimal point neon bulbs 17. The anodes of thenumber tubes 16 are connected in sequence to a positive potential underthe control of the outputs T10 to T1 respectively of the timer circuit12. The highest significant digit in a displayed number is positioned inthe left-hand number tube, which is controlled by the output T10.

One connection to each of the neon bulbs 17 is connected together andthese are connected to the output TD of the timer circuit 12. Thecathodes of the 10 number tubes 16 which are shaped to the same digitare connected together. The other connection of the neon bulb 17 at theleft-hand side of FIG. 1 is connected to the bunched cathode connectionsshowing the digit zero, the other connection of the next neon bulb beingconnected to the bunched cathode connections showing the digit one andso on until the other connection of the 10th neon bulb 17 is connectedto the bunched cathode connections showing the digit '9.

The 10 bunched cathode connections are connected to the outputs of a rowof bistables which form a staticiser 18. The inputs of the staticiser 18are connected to the outputs of a buffer 20 in form of a decade counterwhich is internally interconnected so as to convert a train of pulsesinto the binarycoded decimal equivalent which appears on the output ofthe decade counter. The input of the buffer 20 is connected by a highwayHW8 to the output of a set of gates 22.

When the output F of the function counter is energized, i.e., at thedisplay function position, the contents of the buffer is cleared fromthe buffer 20 into the staticiser 18 at the front edge of each P0 pulseand the staticiser I8 is cleared, i.e., the digit zero line isenergized, at the back edge of each P9 pulse. The buffer 20 has anoutput B0 which is energized, i.e., goes to a positive potential, whenthe buffer 20 stores a digit 0, so that the number cleared from thebuffer 20 stays in the staticiser 18 for nearly the duration of anoutput from the timer circuit 12. The buffer output B0 is connected toan inverter circuit 20a to produce an inverted output [30.

The number tube 16 connected to the output T2 of the timer circuit 12displays the units digits, the number tube 16 connected to the output T3displays the tens digit and so on. The position of the decimal point isgiven by a train of pulses loaded into the buffer 20 when the output TDof the timer circuit 12 is energized and is entered into the staticiser18 and is displayed by the neon bulb 17 at the position corresponding tothe number of pulses in the train, when the next output T1 of the timercircuit is energized. Similarly, if, for example, the digit 4 is to bedisplayed at the tens position, a train of four pulses is entered intothe buffer 20 when the output T2 of the timer circuit is energized andthe binary-coded-decimal equivalent of the digit 4 appears on the outputof the buffer 20. This binary-coded-decimal output is transferred fromthe buffer 20 to the staticiser 18 at the pulse P0 and the digit four isdisplayed on that number tube 16 which is switched on when the output T3of the timer circuit 12 is energized. The digit 4 is cleared from thestaticiser 18 when the pulse P9 occurs at the end of the time in whichthe output T3 is energized. The frequency at which the outputs from thetimer circuit 12 are energized are such that the digits appearing on thenumber tubes 16 and the decimal point appearing on a neon bulb 17 appearto be stationary because of the persistance effect of ocular vision.

An input register 24 has four shift registers 25a, 25b, 25c, and 25deach having 12 digit stages. The input and output of the four shiftregister 25a, 26b and 25d are each connected in a loop with a shiftregister buffer 26 in the form of four bistable circuits which areinternally interconnected to form a decade counter and which act as the13th digit stage. The shift pulse input to four shift registers 25a,25b, 25c and 25d and the shift register buffer 26 are connected by ahighway HWlS to a set of gates 34.

The set of gates 34 provide shift pulses dP9 to the four shiftregisters, 25a, 25b, 25c and 25d and to the shift register buffer 26 sothat the binary-coded-decimal digits in the four shift registerscirculate through the shift register buffer 26 and back to the input ofthe shift registers respectively.

A bistable circuit of the shift register buffer 26 has a carry pulseoutput which is energized when the digit in the shift register buffer 26goes from the count of nine to the count of zero. The carry pulse outputis connected to the input of a carry store 28. The carry store 28comprises a first bistable circuit 30 having the outputs C01 and COT anda second bistable circuit 32 having the output CP0l. The set"connections from the first bistable circuit 30 and the second bistablecircuit 32 respectively are connected to the carry pulse output of theshift register buffer 26. The first bistable circuit 30 is reset by apulse P0 so that the output C01 is energized i.e., is at a positivepotential. A carry pulse from the shift register buffer 26 causes theoutput C01 to be energized. The second bistable circuit 32 is reset by apulse P5, so that the output CP0l is not energized until a carry pulseis received from the shift register buffer 26. A set of gates 36, areconnected by a highway HWS to the input of the shift register buffer 26.

An accumulator register 38 has four l2-stage shift registers 39a, 39b,39c and 39d, a shift register buffer 40 and a carry store 42 aspreviously described for input register 24. The shift pulse inputs ofthe four shift register 39a, 39b, 39c and 39d and the shift registerbuffer 40 are connected by a highway HWl6 to a set of gates 48. Thecarry pulse output of the shift register buffer 40 is connected to theset input of the carry store 42 which comprises a first bistable circuit44 having the outputs C02 and and a second bistable circuit 46.having anoutput CF02. The first bistable circuit 44 is reset by a pulse P0 sothat the output C02 is energized and the second bistable circuit isreset by a pulse P5 so that the output is not energized until a carrypulse is received from the shift register buffer 40. The shift registerbuffer 40 is connected by a highway HWll to a set of gates 50.

Thus in the input register 24 and the accumulator register 38 the shiftregisters and the shift register buffers fonn l3- stage loops aroundwhich pulse patterns circulate in synchronism with the energized outputsof the timer circuit 12. if the input register 24 or accumulatorregister 38 receives 13 shift pulses, the digit in the units or T1 digitstage of the input register 24 or accumulator register 38 is in theshift register buffer 26 or 40 respectively when the output T1 of thetimer circuit 12 is energized. Similarly the tens or T2 digit stage ofthe input register 24 or accumulator register 38 is in the shiftregister buffer 26 or 40 respectively when the output T2 of the timercircuit 12 is energized, and so on.

If one shift pulse to a register is supressed, so that the register onlyreceives 12 shift pulses, the number in the register is moved one placeto the left with respect to the outputs of the timer circuit 12.

If an extra shift pulse is gated into a register with the pulse PS, thenumber in the register is moved one place to the right with respect tothe outputs of the timer circuit 12.

A slip counter 52, which is a four-bistable ripple-through counterinternally interconnected to have 13 count states which are labeled inascending order of count state S0, SD, S1 S1 1, has outputs connected tothe S0 and 811 count states. The outputs to the count states S0 and 811are connected to inverter circuits 52a and 52b respectively to give theoutputs S0 and S l l. The outputs S11, S11 and are used to control logiccircuit gates. The input of the slip counter 52 is connected by ahighway HW6 to a set of gates 54. The slip counter 52 is driven by P9pulses to maintain its energized count states in correspondence with theenergized count state outputs of the timer circuit 12. Shift pulses aresupressed or extra ones gated in through the set of gates 54. The mainpurpose of the slip counter 52 is to keep a record of the amount of slipwith respect of the timer circuit 12, which occurs when a number isshifted in the input register 24 or the accumulator register 38.

A decimal counter 56, which is a four-bistable ripplethrough counterinternally interconnected so as to have count states, has its outputconnected to the set input of an output bistable circuit 60. The inputof the decimal counter 56 is connected by a highway I-IW9 to a set ofgates 58. The output bistable circuit 60 has the outputs D0 and D0. Theoutput bistable circuit 60 is arranged so that the output D0 isenergized when the count in the decade counter 56 goes to or passesthrough the zero count state; the output bistable circuit 60 is reset sothat the out D0 is energized by the next P0 pulse.

The decimal counter 56 holds the count corresponding to the position ofthe decimal point digit of a number stored in the accumulator register38. This decimal point digit is held separately from the other digits inthe accumulator register 38 because the accumulator register is used forcalculation of products and quotients and the whole accumulator register38 is required for holding partial products or partial remainders duringthe calculation. The decimal point digit is also held separately becausethe answer in the accumulator register 38 may need to be repositioned soas to display the most significant digit of the answer in the left-handnumber tube 16 of the visual display 14, and this is more easily done ifthe decimal point digit is held separately.

A bistable circuit 62 having the outputs A and A has the input connectedby a highway I-IW13 to a set of gates 64. A bistable circuit 66 havingthe outputs C and 6 has the input connected by highway I-IW7 to a set ofgates 68, while a bistable circuit 70 having outputs D and D has theinput connected by a highway I-IWlI to a set of gates 72. A bistablecircuit 74 having outputs E and E has the input connected by a highwayI-IW12 to a set of gates 76. A bistable circuit 78 having the outputs Hand H has the input connected by a highway HW14 to a set of gates 80.

The bistable circuit 62 controls which register has its number displayedby the visual display 14; if the bistable circuit 62 is set so thatoutput A is energized, the number stored in the input register 24 isdisplayed; if the bistable circuit 62 is set so that the output A isenergized, the number stored in the accumulator register 38 isdisplayed.

The bistable circuit 66 controls the time at which the input registercan shift with respect to the accumulator register so that the fourbasic arithmetic functions can be performed by the calculating machine.If the bistable circuit 66 is set so that the output C is energized,shift between the registers, can take place; if the bistable circuit 66is reset so that the output C is energized the registers are held sothat shift cannot take place.

The bistable circuit 70 together with the bistable circuit 66 controlsthe number of shift pulses sent through the set of gates 34 and 48 tothe input register 24 and the accumulator register 38 respectively.

The bistable circuit 74 has a control function which occurs during amultiplication operation.

The bistable circuit 78 has a control function which occurs if thenumber stored in the accumulator register 38 becomes negative during anaddition, subtraction or display operation.

The FIG. 2 shows a gating circuit in the form of an AND- logic-gate 90.The operation of the logic gate 90 is controlled by a source ofpotential supplied by the function position F through one of the emitterfollowers 100. The AND-gate 90 is typical of the AND-gate logic gates inthe sets of gates previously described. The output of the emitterfollower 10s is zero volts at the off state and -ZO volts at the onstate and this output is applied through a resistor R of resistance39,000 ohms to the diodes D1, D2, D3 and D4. When the function positionF is not energized, the emitter follower 10c applies a potential of 0volts to the diodes D1 to D4 through the resistor R so that the diodesD1 to D4 are reverse biased to cause the gate 90 operate the input andoutput circuits (not shown) which the diodes D1 to D3 and the diode D4respectively are connected. When the function position F is energized,the emitter follower 10c applies a potential of volts to the diodes D1to D4 through the resistor R so that the diodes D1 to D4 are forwardbiased and the normal AND gate action,

which requires the simultaneous application of a positive potential tothe diodes Dl, D2 and D3 for the AND gate to operate, can be performed.

The FIG. 3 shows in detail the first set of gates 11 shown in FIG. la.The AND-logic-gates 110 to 121 shown as rectangles in the Figures are inthe form of the gate shown in the dotted rectangle in FIGS. 2. ThelO-millisecond delay circuits 111a, 114a and 116a are connected to aninput of the gates l 1 l, 114 and 116 respectively. These delay circuitsoperate by being charged to a potential by the output of the emitterfollower 10c through the resistor R. The delay circuit 113a delays theapplication of the function position F2 to the gate 113. TheNPN-transistor circuit [20a is a delay circuit having two timeconstants: when the transistor is not conducting, the time constant istoo long for the gate 120 to be opened; when the transistor isconducting on the application of the minus signal M, the time constantis short enough for the gate 120 to be opened. The circuit a is aone-quarter second delay circuit. The circuit 11% is an NPN transistorinverter circuit with an OR logic gate connected to the base connectionof the transistor.

The function circuits in the form of other sets of gates shown asrectangles in the FIG. 1 contain AND logic circuit gates similar to thecircuit gate shown in FIG. 2, and other circuits similar to the circuitsshown in FIG. 3. The sets of gates are interconnected with the functioncounter circuit 10 and other sets of gates so that numbers can beentered into the input register 24 and the accumulator register 38through the digit keyboard 5, which numbers are used to performarithmetic calculations selected from those on the function keyboard 8.

The function positions of the function counter circuit 10 operates asfollows:

The display or waiting function position F0 is energized after a delayof one-quarter second by the gate 110, when the calculating machine isswitched on, so that the contents of the input register 24 or theaccumulator register 38 are displayed according to which of the outputsA or A of the bistable circuit 62 is energized. The function position F0is energized also at the end of a function cycle signalled from thedigit keyboard 5 or the function keyboard 8.:

The clear function position F1 clears the number in the input register24 or the accumulator register 38 according to the inputs on the gatescontrolled by this position.

The enter function position F2 enters digits transmitted along thehighway l-IW2 from the digit keyboard 5 into the input register 24.

One function position F3, F4, F5 or F7 is energized when the arithmeticoperation of addition, subtraction, division or multiplicationrespectively, is signalled by pulses transmitted along the highway HW3from the function keyboard 8.

The calculating machine can perform the following routines orsubroutines:

When the calculating machine isswitched on, the function position F0 isenergized after a delay of one-quarter of a second by the gate 110.

If the enter key on the function keyboard 8 is depressed immediatelyafter switch-on the clear and enter signal CE is switched from 0 voltsto +12 volts and the gate 114 pulses, the function counter 10 so thatafter a delay of 10 milliseconds to allow for key bounce, the functionposition F1 is energized and the number in the accumulator register 38is cleared while the number in the input register 24 is circulated. Thegate 112 pulses the function counter 10 so that the function position F2is energized and the gate 119 pulses the function counter 10 so that thefunction position F3 is energized. The number in the input register 24is added to the number in the accumulator register 38 and the resultantin the accumulator register is copied into the input register. The gate118 pulses the function counter 10 so that the function position F0 isenergized.

The operation of the first index key causes the generation of trains offirst index pulses along the highway I-IWZ. A train of first indexpulses is entered into the input register 24. The

generation of the trains of first index pulses causes the input register24 to be cleared before entry of a train of first index pulses intotheinput register 24. The trains of first index pulses cause the gate111, after a delay of 10 milliseconds for key bounce, to pulse thefunction counter 10 so that the function position F1 is energized andthe number in the input register 24 is cleared. The gate 112 then pulsesthe function counter 10 so that the function position F2 is energizedand the first index digit is entered into the input register 24. Thegate 113 pulses the function counter 10 so that the function position Fis energized and the first index digit is displayed on the visualdisplay 14.

The operation of the second index key causes the generation of trains ofsecond index pulses along the highway HW2. The entry of the train ofsecond index pulses follows a similar sequence of operations to theentry of the train of first index pulses except that, as a result of theentry of the first digit, the output of the slip counter 52 is moved onby one output so that the gate 115 is energized almost immediately afterthe gate 111.

The gate 115 pulses the function counter 10 so that the functionposition F2 is energized almost immediately after the function positionF1 has been energized. Because of the earli er operation of gate 115,the gate 112 is not energized and the input register 24 is not clearedby the function position F1 for the entry of the second train of indexpulses. Because of the operation of the slip counter as a result of theentry of the first train of index pulses, the second train of pulses isentered into an immediately lower stage of the input register 24. Theoperation of the third and subsequent index keys are similar to theoperation of the second index key, the trains of index pulses areentered into successive stages of the input register 24.

If the enter key on the function keyboard 8 is depressed after theindexing operation has entered a number into the input register 24, thenumber in the input register 24 is copied into the accumulator register38. The gate 114, 112, 119 and 118 are operated as described for theprevious operation of the enter key. If a further indexing operation isperformed, the first number remains in the accumulator register 38 andthe second number is entered into the input register 24, so that anarithmetic operation can be performed using the first and secondnumbers.

When a function key is depressed on the function keyboard 8, anarithmetic operation is signalled by a train of pulse signalscorresponding to the arithmetic function which are transmitted along thehighway HW3. The gate 116 pulses the function counter 10 off theenergized function output F0 after a lO-millisecond delay to allow forkey bounce of the function key and the gate 117 pulses the functioncounter 10 to energize the function positions F3, F and F7. Thesubtraction function position F4 is energized by using the minus signalsM, which are transmitted when the subtraction function key is depressed,to open the gate 121 so as to pulse the function counter from thefunction position F3 to the function position F4. If the subtractionoperation results in a negative answer the bistable circuit 78 is pulsedby a gate in the set of gates 80 so that the output H is energized inplace of the output H. The bistable circuit 78 stays with the output l-lenergized to display a negative sign on the visual display 14, when theanswer is displayed. When the output H of bistable circuit 78 isenergized, if a further addition operation is signalled, the gate 120pulses the function counter 10 so that the subtraction function positionF4 is energized; and if a further subtraction operation is signalled,the gate 117 pulses the function counter so that the addition functionposition F3 is energized because the gate 121 is closed since the inputif of the gate 121 is now energized. Thus, addition operations becomesubtraction operations and vice versa until the number in theaccumulator register 38 goes positive and the pulse in the set of gates80 pulses the bistable circuit 78 so the output H is energized.

In the multiplication operation the number in the accumulator register38 is the multiplier and the number in the input register is themultiplicand. The product is stored in the accumulator register 38. Themultiplication process consists of entering the tens complement of theleast significant digit in the accumulator register 38 into the buffer20. The number in the input register 24 is added into the accumulatorregister 38 and on each addition the number in the buffer 20 isincreased by one increment. when the buffer 20 reaches the zero countstate, i.e., B0 is energized, after a number of additions equal to theleast significant figure originally in the accumulator register, theinput register 24 shifts one place to left and the tens complement ofthe next highest significant digit of the number in the accumulatorregister 38 is entered into the buffer 20.

This sequence is repeated until the product has been built up in theaccumulation register 38 by successive addition of partial products. Atthe end of the multiplication operation the decimal point position ofthe product is calculated by adding the multiplicand decimal point countto the multiplier decimal point count stored in the decimal pointcounter 56.

If the highest significant figure of the product or partial productspills into the T11 digit stage of the accumulator, when the T11 digitstage is energized, the signal B0 and the signal C02 are togetherenergized so that a gate in the set of gates 76 is energized to pulsethe bistable circuit 74 so as to energize the output E. The output E isan input to a gate of the set of gates 48, and as a result of theenergizing of outputE by the gate in the set of gates 76, the gate inthe set of gates 48 passes the 14th shift pulse to the accumulatorregister 38 to cause the accumulator register to shift one digit stageto the right so that the highest significant figure is moved into theT10 digit stage.

In the division operation, the number in the accumulator register 38 isthe dividend and the number in the input register 24 is the divisor. Thequotient is stored in the accumulator register. The division operationtakes place with the input register shifted to the right with respect tothe accumulator. The division process consists of transferring the mostsignificant digit of dividend (plus one.) to the buffer and thensuccessively subtracting the divisor from the dividend until thedividend goes negative. The divisor is then added back to the dividendand a right shift operation takes place. As the division operationcontinues the quotient is built up digit by digit from the highestsignificant figure of the accumulator register.

Cases of division may occur where the first digit of the divisor is someway down the input register 24. and, in this case, the calculatingmachine would try to calculate a first digit of quotient greater than 9and would spill its answer to the left into the T11 digit stage of theaccumulator register. This case is guarded against by having a conditionin the division routine that the first quotient digit is 0. (This digitis held at T11 and is not displayed.) The first digit of dividend heldat T11 is 0, therefore, the first subtraction of the divisor shoulddrive the buffer 20 to 0 (so that the output B0 is energized) if theabove condition is satisfied. If the condition is not satisfied then agate in the set of gates 48 is energized to add an extra, 14th, shiftpulse at P5 to shift the accumulator register 38 to the right and thedivision routine begins again. Eventually the first quotient digit willbe 0 and the division process proper can continue. 'At the end of thedivision operation the decimal point position of the quotient iscalculatedby subtracting the divisor decimal point count from thedividend decimal point count stored in the decimal point counter 56.

In the addition operation, the number in the input register 24 is addedto the number in the accumulator register 38. The answer is displayed inthe accumulator register. The numbers are aligned before addition byrelative shifting of the input and accumulator registers by a number ofshifts equal to the difference between the decimal point count.

lf, when the numbers are added together, there is a carry into the T11stage of the accumulator, the output CF02 of the carry store isenergized to T11. A gate in the set of gates 48 is energized to pass aP5 pulse as the 14th shift pulse to the accumulator register so as tocause the accumulator register 38 to shift one digit stage to the rightwith respect to the timer cirunit 112. A gate in the set of gates 58 isenergized to pass a P0 pulse to the decimal point counter 56 to move thedecimal point one space to the right.

The subtraction operation is similar to the addition operation and isdone by the usual method of complementary addition. The right shiftoperation for the subtraction operation is identical with the rightshift operation previously described for the addition operation.

The answer to a calculation is stored in and circulates around theaccumulator register 38 and is displayed when the inputs marked F ongates are energized. A digit is shifted into the shift register buffer40 of the accumulator register 38 by a dP9 pulse which occurs at thesame time as the next output of the timer circuit 12 is energized. Agate in the set of gates 50 is energized for the outputs Tl, TD and T2to T10 of the timer circuit 12 and allows l0 oscillator GD pulses(corresponding to the pulses P0 to P9) to circulate the digit in theshift register buffer 40. At the same time a gate in the set of gates 22is shut (since the first bistable circuit 44 was reset by the firstpulse P0) and does not allow oscillator GD pulses to pass into thebufi'er 20. When the digit in the shift register buffer 40 goes through0, a pulse is passed to the first bistable circuit 44 and the secondbistable 46 so that the outputs C02 and CP02 are energized. When theinput C02 is energized the gate in the set of gates 22 allows a numberof oscillator pulses GD equal to the digit in the first register buffer40 to enter the buffer 20. As previously described, the digit in thebuffer is cleared into the staticiser 18 at the next P0 pulse (whichalso resets the first bistable circuit 44) and the digit is displayed onthe visual display 14.

The function positions of the function counter circuit 10 may controlarithmetic operations, program routines or subroutines other than thosedescribed.

The function counter circuit 10 may have any number of count states.

The circuitry associated with the function counter circuit 10 may be somodified that the pulse count stored in the counter circuit can stepfrom any count state directly to any other count state.

What is claimed is:

1. An electronic calculating machine comprising a plurality of functioncircuits for performing a plurality of calculating functions andapparatus for controlling the operation of said function circuits of thecalculating machine, said apparatus including a function counter circuithaving an input for receiving count pulses and a plurality of outputcount states each with an output circuit, a source of function pulses,input gating circuits connected to the input of the counter to gatepulses for counting said counter circuit connected to said source offunction pulses to thereby gate function pulses and cause said counterto attain a predetermined count state in response to the gated functionpulses, function keys connected to the source of function pulses forcontrolling the function pulses coupled from said source of functionpulses to said gating circuits, and control circuits operable from saidcounter connecting outputs from said counter states to respective saidfunction circuits to attain predetermined calculating functions for eachcounter state with corresponding ones of the function circuits.

2. A calculating machine according to claim I, wherein said gatingcircuits include a first set of gate circuits, the outputs of said firstset of gate circuits being connected to the input of the countercircuit, inputs of said set of gate circuits being connected to saidsource of function pulses, and to at least one said output state circuitof the counter circuit so that, when a gate circuit in the first set ofgate circuits is energized to apply a pulse input of at least one pulseto said input of said counter circuit, the counter circuit counts thepulse input so as to move the energized count state by a number of countstates equal to the number of pulses in the pulse input.

3. A calculating machine according to claim 1, wherein said gatingcircuits include several sets of gates, each connected to gate pulses tosaid counter input and each having an output of said counter circuitconnected thereto so as to operate the ate; whereby, when apredetermined count state is energized, t e set of gates connec ed tothe energized count state outputs operates to gate signals and the setof gates connected to the nonenergized count state outputs cannot gatesignals.

4. A calculating machine according to claim 1, wherein said gatingcircuits include a plurality of sets of gate circuits each having aninput circuit responsive to an output state of said counter and eachhaving an output circuit connected to gate pulses to said counter input.

5. A calculating machine according to claim 1, including circuit meanswith buffer circuits, wherein the outputs from the count states of thecounter circuit are connected to the inputs of the buffer circuitsrespectively and the outputs of the buffer circuits are connected to thefunction circuits.

6. A calculating machine according to claim 1, wherein said source offunction pulses comprises a master oscillator providing timing pulses,an input decade counter with 10 outputs which is connected to receiveoutput pulses from said oscillator to divide the oscillator pulses intoa sequence of trains of 10 pulses which appear respectively on said 10outputs of the input decade counter, a function keyboard including aplurality of said function keys each having two connections, each of thefunction keys being connected by one said connection to one respectiveoutput of said input decade counter, a function gate circuit in saidinput gating circuits with an input connected to the other connection ofthe function keys, a function highway line connecting an output from thefunction keys to at least one input of said input gating circuitsconnected to the input of the counter circuit, and pulse durationforming circuits providing when one said function key is operated, thecorresponding output of said input decade counter to said function gatecircuit transmitting along said function highway line a function signaloutput of duration proportional to the position of the pulses of thecorresponding output of the input decade counter.

7. A calculating machine according to claim 6, wherein the functionsignal output transmitted from said function gating circuit is a singlepulse beginning at a reset pulse and ending at the pulse from thecorresponding output of the input decade counter.

8. A calculating machine according to claim 6, wherein said functionkeyboard includes at least some keys each of which is connected by oneconnection to a source of potential and other connection to inputs ofthe set of gates connected to the input of the counter circuit.

9. A calculating machine according to claim 6, including counter resetmeans providing a reset pulse to said function counter and includingmeans to transmit the function signal output from said function gatingcircuit as a train of pulses of number proportional to the position ofthe pulses of the corresponding output of the input decade counter fromsaid reset pulse.

10. A calculating machine according to claim 9, wherein the calculatingmachine includes a digit keyboard including a plurality of digit keyshaving two connections and representing the digits 0 to 9, one circuitconnection of each of the plurality of digit keys is connected to theoutputs of the input decade counter respectively, said means to transmitthe function signal comprising a circuit connecting the input of thedigit gate to the other connections of the digit keys, an output digithighway line connected to at least one input of said input gatingcircuits connected to the input of the function counter and furthercircuits connected so that when a digit key is operated, the output ofthe input decade counter connected to the digit key is transmitted by adigit signal of duration proportional to the digit represented by theoperated digit key.

ll. A calculating machine according to claim 10, including circuit meansproviding that said digit signal is a train of pulses.

12. A calculating machine according to claim 10, including circuit meansproviding that said digit signal output transmitted from the digitgating circuit is a single pulse.

1. An electronic calculating machine comprising a plurality of functioncircuits for performing a plurality of calculating functions andapparatus for controlling the operation of said function circuits of thecalculating machine, said apparatus including a function counter circuithaving an input for receiving count pulses and a plurality of outputcount states each with an output circuit, a source of function pulses,input gating circuits connected to the input of the counter to gatepulses for counting said counter circuit connected to said source offunction pulses to thereby gate function pulses and cause said counterto attain a predetermined count state in response to the gated functionpulses, function keys connected to the source of function pulses forcontrolling the function pulses coupled from said source of functionpulses to said gating circuits, and control circuits operable from saidcounter connecting outputs from said counter states to respective saidfunction circuits to attain predetermined calculating functions for eachcounter state with corresponding ones of the function circuits.
 2. Acalculating machine according to claim 1, wherein said gating circuitsinclude a first set of gate circuits, the outputs of said first set ofgate circuits being connected to the input of the counter circuit,inputs of said set of gatE circuits being connected to said source offunction pulses, and to at least one said output state circuit of thecounter circuit so that, when a gate circuit in the first set of gatecircuits is energized to apply a pulse input of at least one pulse tosaid input of said counter circuit, the counter circuit counts the pulseinput so as to move the energized count state by a number of countstates equal to the number of pulses in the pulse input.
 3. Acalculating machine according to claim 1, wherein said gating circuitsinclude several sets of gates, each connected to gate pulses to saidcounter input and each having an output of said counter circuitconnected thereto so as to operate the gate; whereby, when apredetermined count state is energized, the set of gates connected tothe energized count state outputs operates to gate signals and the setof gates connected to the nonenergized count state outputs cannot gatesignals.
 4. A calculating machine according to claim 1, wherein saidgating circuits include a plurality of sets of gate circuits each havingan input circuit responsive to an output state of said counter and eachhaving an output circuit connected to gate pulses to said counter input.5. A calculating machine according to claim 1, including circuit meanswith buffer circuits, wherein the outputs from the count states of thecounter circuit are connected to the inputs of the buffer circuitsrespectively and the outputs of the buffer circuits are connected to thefunction circuits.
 6. A calculating machine according to claim 1,wherein said source of function pulses comprises a master oscillatorproviding timing pulses, an input decade counter with 10 outputs whichis connected to receive output pulses from said oscillator to divide theoscillator pulses into a sequence of trains of 10 pulses which appearrespectively on said 10 outputs of the input decade counter, a functionkeyboard including a plurality of said function keys each having twoconnections, each of the function keys being connected by one saidconnection to one respective output of said input decade counter, afunction gate circuit in said input gating circuits with an inputconnected to the other connection of the function keys, a functionhighway line connecting an output from the function keys to at least oneinput of said input gating circuits connected to the input of thecounter circuit, and pulse duration forming circuits providing when onesaid function key is operated, the corresponding output of said inputdecade counter to said function gate circuit transmitting along saidfunction highway line a function signal output of duration proportionalto the position of the pulses of the corresponding output of the inputdecade counter.
 7. A calculating machine according to claim 6, whereinthe function signal output transmitted from said function gating circuitis a single pulse beginning at a reset pulse and ending at the pulsefrom the corresponding output of the input decade counter.
 8. Acalculating machine according to claim 6, wherein said function keyboardincludes at least some keys each of which is connected by one connectionto a source of potential and other connection to inputs of the set ofgates connected to the input of the counter circuit.
 9. A calculatingmachine according to claim 6, including counter reset means providing areset pulse to said function counter and including means to transmit thefunction signal output from said function gating circuit as a train ofpulses of number proportional to the position of the pulses of thecorresponding output of the input decade counter from said reset pulse.10. A calculating machine according to claim 9, wherein the calculatingmachine includes a digit keyboard including a plurality of digit keyshaving two connections and representing the digits 0 to 9, one circuitconnection of each of the plurality of digit keys is connected to theoutputs of the input decade counter respEctively, said means to transmitthe function signal comprising a circuit connecting the input of thedigit gate to the other connections of the digit keys, an output digithighway line connected to at least one input of said input gatingcircuits connected to the input of the function counter and furthercircuits connected so that when a digit key is operated, the output ofthe input decade counter connected to the digit key is transmitted by adigit signal of duration proportional to the digit represented by theoperated digit key.
 11. A calculating machine according to claim 10,including circuit means providing that said digit signal is a train ofpulses.
 12. A calculating machine according to claim 10, includingcircuit means providing that said digit signal output transmitted fromthe digit gating circuit is a single pulse.